This application claims the benefit of Korean Patent Application No. 2001-35662, filed on Jun. 22, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
This invention relates to an electro-luminescence display (ELD), and more particularly to an electro-luminescence panel that is capable of improving a picture quality.
2. Discussion of the Related Art
Recently, there have been developed various flat panel display devices reduced in weight and bulk that are capable of eliminating disadvantages associated with cathode ray tubes (CRTs). Such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electro-luminescence (EL) panel, etc.
Studies for heightening a display quality of the flat panel display device and for providing the flat panel display with a large-scale screen have been actively made. The EL panel in such display devices is a self-emission device. The EL panel excites a fluorescent material using carriers such as electrons and holes, etc. to display a video image. The EL panel has advantages in that a low direct current voltage driving is possible and a response speed is fast.
As shown in FIG. 1, such an EL panel includes gate lines GL and data lines DL arranged in such a manner to cross each other, and pixel elements 108 arranged at crossings between the gate lines GL and the data lines DL. Each of the pixel elements 108 is driven when a gate signal on the gate line GL is enabled, thereby generating light corresponding to the amount of current of the pixel signal on the data line DL.
Further, the EL panel 104 includes current drivers 106 connected to the data lines DL. Each of the current drivers 106 control the current flowing from pixel elements 108, via the data line DL, into itself in response to a pixel signal, thereby applying the pixel signal to each pixel element 108. The current driver 106 allows electric charge current to flow in the pixel elements 108. A current signal which changes in accordance with the pixel signal flows in the pixel elements 108 with the aid of the current driver 106.
The gate lines GL of the EL panel 104 is connected to a gate driver 100 while the current drivers 106 are connected to the data driver 102. The gate driver 100 sequentially drives the gate lines GL. The data driver 102 applies pixel voltage signals for one line to the current drivers 106. Each of the current drivers 106 converts a pixel voltage signal from the data driver 102 into a backward pixel current signal, and applies the converted pixel current signal to the pixel element 108. In other words, the current driver 106 controls the amount of current on a current path going through the data line DL from the pixel element 108, thereby increasing a maximum amount of current at the pixel element 108 and a difference in the amount of current according to a gray scale level. As a result, the EL panel 104 is capable of displaying a gray scale picture.
Referring to FIG. 2, the pixel element 108 includes an EL cell (ELC) connected to a first low voltage line FVL, and an EL cell driving circuit 110 connected between the EL cell (ELC) and the data line DL. The first low voltage line FVL can be connected to a ground voltage source GND, or to the first low voltage source generating a negative voltage. The EL cell driving circuit 110 applies a forward current signal which changes in accordance with a backward amount of current on the data line DL to the EL cell (ELC) in a time interval when a gate signal on the gate line GL is enabled. To this end, the EL cell driving circuit 110 includes third and fourth PMOS TFTs Q3 and Q4 connected to form a current mirror among the EL cell (ELC), a first node N1 and a supply voltage line VDDL, and a capacitor C connected to a second node N2 to which gate electrodes of the third and fourth PMOS TFTs Q3 and Q4 are commonly connected and the supply voltage line VDDL.
The capacitor C charges a signal current on the data line DL when the supply voltage line VDDL is connected to the data line DL, and applies the charged signal current to the gate electrodes of the third and fourth PMOS TFTs Q3 and Q4. The third PMOS TFT Q3 is turned on by a signal current charged in the capacitor C, thereby applying a supply voltage VDD on the supply voltage line VDDL to the EL cell (ELC). At this time, the third PMOS TFT Q3 varies its channel width depending upon an amount of signal current charged in the capacitor C, thereby controlling the amount of current coupled from the supply voltage line VDDL to the EL cell (ELC). Then, the EL cell (ELC) generates light corresponding to the amount of current applied, via the third PMOS TFT Q3, from the supply voltage line VDDL. The fourth PMOS TFT Q4 also controls the current flowing from the supply voltage line VDDL into the data line DL to thereby determine the amount of current flowing into the EL cell (ELC) via the third PMOS TFT Q3.
Further, the EL cell driving circuit 110 includes first and second PMOS TFTs Q1 and Q2 which commonly respond to the gate signal on the gate line GL. The first PMOS TFT Q1 is turned on in a time interval when a low logic of gate signal is applied from the gate line GL, thereby connecting a source electrode of the first PMOS TFT Q1 connected to the first node N1 to the data line DL. In other words, the first PMOS TFT Q1 plays the role of forming a current path extending from the supply voltage line VDDL, via the fourth PMOS transistor Q4, the first node N1 and itself, into the data line DL in response to the low logic gate signal. The second PMOS TFT Q2 is also turned on in a time interval when the low logic gate signal from the gate line GL is applied to a gate electrode thereof, thereby connecting the gate electrodes of the third and fourth PMOS TFTs Q3 and Q4, via the second node N2 and the first node N1 connected to one terminal of the capacitor C, to the data line DL. In other words, the first and second PMOS TFTs Q1 and Q2 is turned on in a time interval when the gate signal on the gate line GL remains at a low logic to connect the data line DL to the supply voltage line VDDL as well as the second node N2, thereby charging a charge amount (or a signal current) corresponding to the amount of current flowing in the data line DL.
The first PMOS TFT Q1 of such an EL cell driving circuit 110 is turned on simultaneously with the second PMOS TFT Q2 having the same threshold voltage when the gate signal is changed from a low logic into a high logic. Thus, a kick-back phenomenon occurs in which a charge amount charged in the capacitor C is leaked at the falling edge of the gate signal. As a result, the EL cell (ELC) fails to accurately generate light corresponding to the amount of current on the data line DL, thereby causing picture deterioration or distortion.
Accordingly, the present invention is directed to an electro-luminescence pixel that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An advantage of the present invention to provide an electro-luminescence panel that is capable of improving picture quality.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an electro-luminescence panel according to one embodiment of the present invention includes a plurality of gate lines; a plurality of data lines crossing the gate lines; a plurality of electro-luminescence cells arranged at crossings between the gate lines and the data lines; a plurality of capacitors for charging signals from the data lines; and first and second switches for applying signals on the data lines to the capacitors in response to gate signals supplied via the gate lines, said first and second switches having threshold voltages set to be different from each other.
In the electro-luminescence panel, the first switch has a gate terminal connected to the gate line, a source terminal connected to the data line and a drain terminal connected to a source terminal of the second switch.
The second switch has a gate terminal connected to the gate line, a source terminal connected to a drain terminal of the first switch and a drain terminal connected to the capacitor.
The threshold voltage of the first switch is set to be lower than that of the second switch.
A difference between the threshold voltage of the first switch and the threshold voltage of the second switch is more than about 0.5V.
The electro-luminescence panel further includes a third switch for applying signals on the data lines to the electro-luminescence cells in response to the signal current charged in the capacitor; and a fourth switch for controlling a current applied to each electro-luminescence cell.
The electro-luminescence panel further includes a third switch connected between the electro-luminescence cell and the capacitor; and a fourth switch connected to the third switch to form a current mirror.
Each of first to fourth switches includes a thin film transistor of same polarity channel.
First and second switches include thin film transistors having polarity channels different from each other, and third and fourth switches include thin film transistors having the same polarity channel.
A gate insulating film of the second switch has a larger thickness than a gate insulating film of the first switch.
A protective layer of the second switch has a larger thickness than a protective layer of the first switch.
An inter-layer insulating film of the second switch has a larger thickness than an inter-layer insulating film of the first switch.
A gate electrode of the second switch has a single-layer structure while a gate electrode of the first switch has a multi-layer structure.
Source and drain electrodes of the second switch have a single-layer structure while source and drain electrodes of the first switch have a multi-layer structure.
Source and drain electrodes of the second switch are made from a material different from those of the first switch.
A semiconductor layer of the second switch is made from a material different from that of the first switch.
A concentration of ions injected into a semiconductor layer of the second switch is set to be higher than a concentration of ions injected into a semiconductor layer of the first switch.
A semiconductor layer of the second switch includes hydrogen impurities.
A semiconductor layer of the second switch undergoes a surface treatment using plasma.
A lower substrate of the first switch has a crystallization direction different from that of the first switch.
A gate electrode of the second switch is made from a material different from that of the first switch.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.